In a dynamic random access memory (DRAM) that stores the information by holding electric charge in a capacitor, a refresh operation is needed for data retention. In a DRAM, the refresh period needs to be made shorter at higher temperatures. Conversely, at lower temperatures, the data retention time is prolonged, and hence the refresh period may be made longer to reduce the current consumption of a DRAM. Such a configuration is therefore used in which the DRAM is provided with the function of outputting a temperature code indicating a current chip temperature and in which an apparatus that mounts the DRAM thereon causes a change in the period of issuance of a refresh command to the DRAM in dependence upon a temperature code output from the DRAM.
Patent Document 1 discloses a configuration as a technique related with a semiconductor device provided with a temperature measurement circuit. In this configuration, a first current (PTAT) whose current level rises with rise in temperature and a second current (CTAT) whose current level falls with rise in temperature are output by a temperature sensor to a comparator in response to a first current control signal (CTRLS1) or a second current control signal (CTRLS2). The comparator outputs a temperature signal (TS) having the information as to whether the temperature in the semiconductor device is higher or lower than a reference temperature. A holding unit saves the temperature signal from the comparator and subsequently outputs the so saved temperature signal to a controller. The controller then causes the current level of the first current (PTAT) or the second signal (CTAT) to be changed in response to the temperature signal (TS) output from the holding unit to generate the first current control signal (CTRLS1) or the second current control signal (CTRLS2) that control the reference temperature. The Patent Document 1 thus comprises a single temperature sensor/comparator, a holding unit comprises a plurality of latch circuits, and a plurality of switching circuits used to switch between the single temperature sensor/comparator circuit and a plurality of latch circuits. Outputs of a plurality of result latch circuits from LSB to MSB are combined together to yield a final result of temperature measurement with high accuracy.
Patent Document 2 discloses a configuration of controlling the self-refresh period in which the refresh period is adjusted in keeping with a change in temperature to reduce current consumption. In this configuration, temperature measurement is made at each maximum value time of a preset period to render the refresh period variable. Specifically, with Patent Document 2, a first period control signal (TS) is generated in response to a self-refresh start signal (SRS) or a self-refresh end signal (SRS). A sampling clock (SCLK) is generated in response to a clock signal (MSB) generated by the self-refresh start signal (SRS). A temperature sensor operates in response to the sampling clock (SCLK) to sense the temperature of the semiconductor memory device, and a corresponding second period control signal (TS) is generated. A period controller controls the self-refresh period in response to the first period control signal (TS) and the second period control signal (TS). The period controller decides the multiplication factor of the period clock signal (TCLK) applied from the clock generator in response to the period control signal (TS) to output the resulting signal as a refresh period signal (RS).
Patent Document 3 discloses a configuration of measuring the temperature in a semiconductor device in which a memory controller delivers a sampling clock to a memory device, which memory device measures the temperature in response thereto. The memory controller operates as an ODTS (On-Die Thermal Sensor) which is a temperature information output device that accurately updates the temperature information irrespectively of the DRAM's operating mode. Specifically, Patent Document 3 discloses a configuration comprising a temperature information code generation means and a flag signal logic decision means. The temperature information code generation means measures the temperature of the inside of the semiconductor device, in response to first and second enable signals, to generate a temperature information code having the information on the measured temperature. The flag signal logic decision means generates a plurality of first flag signals, having the temperature information, in response to the first and second enable signals, to decide whether the first flag signal has a preset logic level value or a variable logic level value.    [Patent Document 1] JP Patent Kokai JP-A-2005-031077    [Patent Document 2] JP Patent Kokai JP-A-2006-040527    [Patent Document 3] JP Patent Kokai JP-A-2008-083021